| BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| BODY LENGTH | 0.330 INCHES MINIMUM AND 0.350 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | TO-88 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, MASTER SLAVE |
| FEATURES PROVIDED | HERMETICALLY SEALED AND W/CLOCK AND MONOLITHIC AND POSITIVE OUTPUTS |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| OVERALL WIDTH | 0.400 INCHES NOMINAL |
| MAXIMUM POWER DISSIPATION RATING | 72.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |