| BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-86 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, OR-NOR |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND NEGATIVE OUTPUTS AND HIGH SPEED AND INTERNALLY COMPENSATED |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| MAXIMUM POWER DISSIPATION RATING | 95.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | EMITTER-COUPLED LOGIC |
| STORAGE TEMP RANGE | -65.0 TO 175.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TIME RATING PER CHACTERISTIC | 4.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -10.0 VOLTS MINIMUM POWER SOURCE AND 0.0 VOLTS MAXIMUM POWER SOURCE |